This is a Verilog implementation of the 6809 processor. This implementation adds extra features to the 6809 in order to support 32 bit addressing. Many of the peripheral softcores I've created depend on 32 bit addressing. The extra features include a 32 bit program counter and 32 bit indirect addressing.
A couple of new instructions have been added to support the 32 bit program counter addressing.
RTF is a far return from subroutine.
JSR FAR jumps to a subroutine with a far address, and
JMP FAR jumps to a far address.
Interrupts store a full 32 bit program counter. The RTI instruction restores a 32 bit program counter from the stack.
The FAR prefix has been added as an indicator to use far addresses instead of extended addresses. The assembler will automatically output this prefix where needed if the indicated address is more than 16 bits. The FAR prefix can be applied to extended address mode instructions and also applied for indirect addresses.
The following loads a 16 bit value from a text controller located at the 32 bit address $FFFA0000.
LDD FAR $FFFA0000 ; load from text controller register
LDD $FFFA0000 ; the assembler will automatically output a FAR prefix
When applied to indirect addresses, the indirect address fetched from memory is used as a far address. So a four byte address is fetched from memory in the following case:
LDD far [$1000]
fcd $FFDC0600 ; address of LEDs
Note that indirect addresses must be within the first 64k bank of memory. The far prefix does not apply to the address $1000 above, but to the address fetched from address $1000 above.
Note also that the assembler can't tell whether or not the address is a far address, so the FAR prefix has to be inserted manually in the code where required.
The FAR prefix may also be applied to the PSH/PUL instructions to indicate that the PC address is four bytes in length, otherwise a PSH/PUL only transfers the low order 16 bits of the PC as usual. As mentioned earlier, interrupts and the RTI instruction always transfer the full 32 bit program counter.
The Outer Prefix
As further support for 32 bit addressing a new outer indexed indirect addressing mode has been added to the processor. This addressing mode is invoked using another instruction prefix which is automatically output by the assembler. Outer indexing of a indirect address is typically more useful than inner indexing because it allows an indexing operation similar to regular indexed addresses.
In outer indexed indirect addressing the index register is applied to the address fetched from memory after the indirect address is fetched. Contrasted with regular(inner) indexed indirect addressing where the index is applied before the indirect address is fetched from memory.
Outer Indexing: ldd [AnAddress],y
An address is fetched from address AnAddress, then Y is added to the fetched address to form the final address from which the data is fetched.
Inner Indexing: ldd [AnAddress,y]
An address is fetched from address AnAddress+y which is then used to fetch the data.
Interrupt subroutines must be located in the first 64k bank of memory as the 6809 allows only a 16 bit address vector. You can always do a far jump to an interrupt routine in another bank if required.
As coded, the core accepts a 32 bit interrupt vector through a private interrupt vector bus during interrupt processing. The logic works as follows:
if (external vector is non zero)
set vector to external vector
use regular 6809 vector.
The external vector is expected to be supplied by a priority interrupt controller.
RTF6809 Instruction Set Table
John Kent's 6809 core in VHDL.
A09 Assembler for the 6809/6800. A hacked version of this assembler is being used to develop code for the RTF6809.