FPGA Cores Available for Viewing

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Photo of 1977 AM9551 below

These cores are presented here for your viewing pleasure. What is a core ? - Cores are the kind of programs that are used to make digital computer chips. If you've ever wondered how did they do that.... One way of doing things is presented here. Hopefully the cores are easy to read and easy to understand (they also work - unless otherwise stated). They look the best in a color syntax hi-liting editor. I plan on sticking to all original work.

All cores are written in Verilog (it's my favorite paint).

License required for commercial use. 

 

CPU Time Keeping Video Audio Keyboard Memory  
   
Core Name Description Download
Peripherals
kfc6532

6532 RAM/IO/Timer

one extra clock divisor option (/16384)  for higher frequency clock operation

dac121s101

12 bit D to A converter interface core

(tested, working)

tone sample (1.5s)

ask!
rawATA 16 bit raw ATA interface - connects SoC to ATA bus rawATA.v
rand 32 bit random number generator more rand.v
bcUart advanced uart peripheral, harmonic synthesis baud rate generator (use any clock!), fifo's, programmable frame formats, etc. nope
RAM
arRam1rw Asynchronous readback / synchronous write RAM, useful as a register memory. Single read/write port arRam1rw.v
arRam1rw1r Asynchronous readback / synchronous write RAM, useful as a register memory. read/write port plus second read port arRam1rw1r.v
Arithmetic    
addsub adder / subtracter addsub.v
carry computes carry for addsub carry.v
overflow computes overflow for addsub overflow.v
rolx1 rotate or shift left 0 to 3 bits rolx1.v
rolx4 rotate or shift left 0, 4, 8 or 12 bits rolx4.v
rolx16 rotate or shift left 0, 16, 32 or 48 bits rolx16.v
rol rotate or shift left 0 to 63 bits rol.v

shiftAndMask

Shifting and masking unit. Shifts and  rotates left or right and bit masking. 19 ns ! 170 slices for full 32 bit operations.

ask!

Other
logicUnit performs one of eight different logic operations logicUnit.v

edge_det

detects edges (positive, negative or either) on signals

edge_det.v

critical reset signal generator

Used to create local reset signals for circuits where reset signal timing is critical, for example in state machines. As noted in FPGACPU discussions.

critical_reset_gen.v

Variable Tap Delay Line

A delay line with a variable tap point.

Infers a shift register / multiplexer (dynamic shift register - DSR) core. Parameterized width.

vtdl.v

fifo16s

New and improved over bc_fifo16s (same signals)

16 entry deep fifo. Parameterized width, status outputs.

fifo16s.v

updown_counter

Counts up or down, parameterized width

updown_counter.v