PS2Kbd PS2 Compatible Keyboard / Mouse Interface Core

2010 Robert Finch


PS2Kbd is an PS2 compatible keyboard / mouse interfacing core allowing a PS2 keyboard or mouse to easily be interfaced to a system on programmable (SOPC) chip bus. The core supports both reading and writing to the keyboard.

Both the keyboard and mouse use the same hardware interface and serialize data in the same fashion; however the protocol used by the keyboard and mouse are different. This module does not handle the protocol differences but instead presents a raw data interface. Management of the protocol is left up to driver software or additional hardware, which is probably the best place for it to be handled as it reduces the hardware complexity and size. This also means a keyboard or mouse may be connected to any port via this interface, provided the software is able to detect the difference. Unlike many serial communication interfaces, there is no buffering of the data because it is not required due to the slow speed of the interface and the manner in which the PS2 interface works. Read operation is expected to be interrupt driven or otherwise managed via the presence of the irq signal. Write (transmit) operation is expected to be driven using a timed system due to the slow speed; although the transmit operation may be monitored with the status register.

PS2Kbd is composed of a single module and uses a simple bus interface which is WISHBONE compatible, and easily adapted to any SoPC bus. This module is a basic raw interface that converts between the serial keyboard / mouse protocol and a byte wide register made available to the SoPC. No attempt is made to process the bytes received or transmitted on the interface. This allows the core size to be small and adaptable to other devices which also use the PS2 serial interface.

To get a scan code from the interface, first check the interrupt bit in the status register to see if a scan code is available, then read the scancode if one is available. Note that reading the receive register will clear the register of any character currently being received. The interface prevents the keyboard from sending more characters until the last character is read from the interface.

There are several sources of info on the www describing the operation of the PS2 keyboard / mouse interface (for example):

All signals are active high unless otherwise noted.

Download - PS2kbd.v


Performance values are approximate (Spartan 2e-6):

Speed: 90MHz / 176 LUTs / 96 slices


module PS2Kbd(rst_i, clk_i, cyc_i, stb_i, wr, adr, din, dout, ack, kclk, kd, irq);
parameter pClkFreq;

Signal Description
rst_i This signal is normally connected to the system reset signal. It resets the keyboard interface forcing it to the idle state.

rst is sampled on the positive edge of the clock

clk_i this is usually connected to the system clock and is used as a base timing clock. This clock should be at least 100kHz to ensure proper operation of the keyboard interface.
cyc_i indicates that a valid bus cycle is taking place. The core will not respond to the bus unless this signal is active.
stb_i This strobe signal also indicates that a valid bus cycle is taking place
ack_o This signal indicates that the core has processed the bus transaction (it is the logical and of cyc_i and stb_i).
we_i This signal is used to signify a write operation to the keyboard interface.
adr This is a single address bit used to address one of two available keyboard registers. (Registers are described below).
dat_i This is the eight bit data input bus to the keyboard interface.
dat_o This is the eight bit data output bus from the keyboard interface.
irq This is an active high signal that indicates when a scan code is available to be read from the keyboard interface. It will remain high until the keyboard transmit / receive register is read.
kclk This is a bi-directional tri-state connection to the keyboard clock line. An external pullup resistor is required.
kd This is a bi-directional tri-state connection to the keyboard data line. An external pullup resistor is required.
pClkFreq Use this parameter to specify the clock (clock enable) frequency in hertz. Default setting of 28636360. (Hz). This core uses this value to set the values required for the debounce timeout (5 us) and the clock hold (100us).

Register Description

Reg. No. Function Description
0 transmit / receiver buffer write - write to transmit buffer
read - read received character, then clear buffer
1 read status / write clear transmitter

bit 7 = interrupt status
bit 6 = 1= transmit complete, 0= transmit incomplete

bit 5 = transmit acknowledge bit from keyboard - the keyboard sets this bit in response to a command from the host.
bit 5,4,3,2,1 = reserved
bit 0 = 1=parity error

WISHBONE Compatibility Datasheet

The PS2kbd core may be directly interfaced to a WISHBONE compatible bus. When interfaced to a WISHBONE bus the clock enable signal (ce) should be tied high.


WISHBONE Datasheet

WISHBONE SoC Architecture Specification, Revision B.3





General Description:

PS2 keyboard / mouse interface

Supported Cycles:




Data port, size:

Data port, granularity:

Data port, maximum operand size:

Data transfer ordering:

Data transfer sequencing

8 bit

8 bit

8 bit

Little Endian

any (undefined)

Clock frequency constraints:


Supported signal list and cross reference to equivalent WISHBONE signals

Signal Name:



















Special Requirements: