vgavic Core

2010 Robert Finch


vgavic is a video interface circuit for use within a SoC to interface the system to a VGA compatible display device. The exact capabilities depend on the characteristics of the system it is used in (memory bandwidth, memory capacity, clock frequency).

VGA Video Interface Circuit with the following features:


programmable video memory address


programmable display area


programmable border area


programmable character sets / glyphs


programmable color depth 1,2,3,4, or 6 bits


horizontal and vertical smooth scrolling


raster, vertical  blank, sprite collision interrupts


RAM usage varies from 240B to 300kB


independent horizontal and vertical resolution control


max 640 x 480 x 64 color display (300k)


min 80 x 60 x 2 color display (600)


16 entry 6 bit color palette RAM allowing selection of up to 16 different colors from a palette of 64 (used when color depth is four bits per pixel or less)


eight/four 24 x 21, 64 color sprites


programmable sprite width and height


alpha blending sprite capability


active display memory bandwidth usage from 3.125% to 25% (1/32 to 1/4 cycles) (25.175MHz bus cycle)


linear bitmapped or text mode display

Text Mode

Text mode supports up to 65536 different character glyphs / codes. The maximum glyph code may be set in a register (reg. 13)  to prevent the controller from accessing memory outside of the glyph table when a limited number of glyphs are used. Each character in text mode has a foreground and background color. Text memory has the following layout. It is possible to map the entire screen with different text mode characters, program the glyphs, and use text mode as if it were an additional bit-mapped mode. In this mode each bit in the glyph represents one of two different colors, determined from the text mode cell. The color depth may be set for text mode up to four bits per pixel. In this case the first two colors are read from the text mode cell, the remaining colors are determined from the color palette. The bits in a glyph are grouped together when the color depth is set greater than one bit per pixel. Text mode determines the screen address in memory from the video memory address register.

The glyph width may also be controlled. However setting the glyph width too low will result in display problems as the controller will be unable to fetch data from memory at the resulting fetch rate. Glyph width may be set up to sixteen pixels. The controller reads either a byte or a half-word (sixteen bits) as needed for the glyph. The default glyph width is set to seven pixels. When oddball glyph widths are chosen (not 8/16) extra bits in the byte / half-word are discarded.

Glyph height may also be controlled by bits in register 2. The controller assumes a limited number of memory layouts for glyphs in order to simplify the address calculation. The glyph table is either one or two bytes wide, and either eight or sixteen scan lines deep for each glyph. The glyph is pulled from memory cells as needed. A 12 x 12 character glyph will use 32 bytes of memory (16 bits by 16 scan lines). The default height is eight scan lines.

Text Mode Cell

31                    24 23                    16 15                                                  0
background color foreground color

character code


Color Codes

Foreground and background color bytes

7 6 5 4 3 2 1 0
flash p r1 r0 g1 g0 b1 b0

Bitmapped Mode

Bitmapped mode displays memory in linear sequence. Bits are grouped as a unit to represent colors as needed for the selected color depth. For color depths less than five bits per pixel, the bit group indexes into the color palette area to determine which color to display. When six bits or more are selected for the color depth the bits directly represent RGB values, with two bits each for red, green and blue.

Mixed Mode

It is possible to have the controller switch from bitmapped mode to text mode automatically at any scan line of the display.


Smooth Scrolling

Both the border area, and the memory fetch region may be controlled by registers in the controller. Changing the border area without changing the fetch area will result in some characters being hidden from the screen. By combining this with modification of the memory fetch region, smooth scrolling can be effected. Note that memory fetch must normally begin a number of pixels (depending on the video mode) before display occurs. This is due to pipelining in the video controller (the controller has to have the data available in its pipeline before it can start displaying it).

Display enable - there is a global display enable that may be used to disable display output and corresponding memory fetches.



Sprites are image areas that may be controlled independently from the remainder of the screen. Sprites are available in all display modes. Sprites normally appear in front of other images on the screen. However if bit 6 (the sprite priority bit) of the screen color is set, the sprite will appear behind these colors. Sprites may also be designated as alpha blenders, in this case the low order two bits of the color determine the amount of blending 0 = black, 1 = 33%, 2 = 66% and 3 = 100%.

The video controller contains a up to 4kB dual port memory to contain the sprite image data. This may be mapped into the SoC using a separate chip select. Each sprite image is allocated 512 bytes of memory.

address 7 6 5 4 3 2 1 0  
0 - 511 - - r1 r0 g1 g0 b1 b0 sprite 0
512 - 1023 - - r1 r0 g1 g0 b1 b0 sprite 1
1024 - 1535 - - r1 r0 g1 g0 b1 b0 sprite 2
1536 - 2047 - - r1 r0 g1 g0 b1 b0 sprite 3
2048 - 2559 - - r1 r0 g1 g0 b1 b0 sprite 4
2560 - 3071 - - r1 r0 g1 g0 b1 b0 sprite 5
3072 - 3583 - - r1 r0 g1 g0 b1 b0 sprite 6
3584 - 4095 - - r1 r0 g1 g0 b1 b0 sprite 7

Display Priority

Sprites have a fixed display priority with respect to one another. Sprite 0 appears in front of all other sprites, Sprite 1 has the next highest priority and so on down the line. Sprites appear behind pixels where bit 6 of the pixel color is set to zero, otherwise they appear in front of other pixel colors. However sprites also appear in front of the color defined as the background color. The background color is set in the background color register (register 12).


Both the width and the height of the sprite may be set by setting values in the sprite width and height registers. The product of the width and height should not exceed 511. Both the width and height may vary from 1 to 63 pixels. Sprites default to a size of 24 x 21 for width and height respectively. Sprite may be made either double width or double height or both double width and double height. For double width or double height the size of the displayed pixels is doubled (there are still the same number of pixels for the sprite, they are just twice as large). Sprites may be positioned at any location on (or off) the screen. They will be clipped by the border.

Timing Controls

VGA timing characteristics are completely programmable. However the critical timing controls are locked by default. Timing is set up for a standard 640 x 480 VGA display. In some circumstances it may be necessary to change the timing controls, for instance in order to support a higher resolution display.

Memory Addressing / Memory Bandwidth Usage

This core assumes that the memory system will be able to provide data at a high enough rate so that a line buffer is unnecessary. Video memory access is pipelined and buffered so that a request for more data begins when the data in the last stage of the pipeline has been used. The pipeline provides data needed for display. As the pipeline is supplying the data more data is being supplied to the pipeline by the memory system. Generally, it will take several clock cycles for the controller to use the current data of the last pipeline stage; the memory system must be able to supply new data within this window. For instance, in 40 x 25 text mode with a 28MHz clock there are 16 clock cycles within which to fetch new data. In this time frame the controller needs to perform 3 memory reads. In 320 x200 x 6 bpp the controller needs to read from memory once every four clock cycles.


Register Description

Reg. No. 15                               0 Function Description
0 aaaaaaaa aaaaaa00 video base address low contains the lower sixteen bits of the address of the screen; must be a word address
1 aaaaaaaa aaaaaaaa video base address high contains the upper sixteen bits of the address of the screen
2 aaaaa - wwww hhhhhh character glyph address low; character height in scan lines, character width in pixels contains bits 15 - 11 of the character glyph table address; bits 10 - 15 are assumed to be zero

and the number of vertical scan lines per character. Currently only two heights are supported 8 and 16 scan lines

3 aaaaaaaa aaaaaaaa character glyphs address high contains the high order sixteen bits of the character glyph table address
4 t --- cccc vvvv -hhh resolution control register resolution control
---- cccc vvvv -hhh
hres hhh vres vvv
000 = 640 000 = 480
001 = 320 001 = 240
010 = 213 010 =160
011 = 160 011 = 120
100 = 128 100 = 96
101 = 106 101 = 80
110 = 91 110 = 68
111 = 80 111 = 60

cccc = color depth (bits per pixel)
use only 1,2,3,4 or 8

5 g---rvbs -----VBS irq enable / pending

V - enable vertical blank interrupts

B - enable sprite-background collision interrupt

S - enable sprite-sprite collision interrupt

v - vertical interrupt is pending

b - sprite-background collision interrupt is pending

s - sprite-sprite collision interrupt is pending

r - raster interrupt is pending

g - any interrupt is pending

6 ----R - rrrrrrrrrr irq enable / raster compare

R - enable raster compare interrupts


rrr... raster value for comparison

7, 9- 31 reserved   these registers are reserved
8 -------- eeeeeeee sprite enable register acts as display enable for sprites
9 -------- cccccccc sprite-sprite collision register indicates which sprites are colliding
10 -------- cccccccc sprite-background collision register indicates which sprites are colliding with the background
12 ---- nnnnnnnnnnnn text mode enable row row (scan line) at which text mode is enabled. Allows mixed text / graphics screens.
13 nnnnnnnn nnnnnnnn glyph count register sets limit on the largest character code in use
14 -------- --cccccc background color this register sets the color considered to be the background color
15 g ------- -- cccccc global display enable; border color This register controls the color of the border. The global display enable bit turns the display on or off and prevents the video controller from performing memory accesses while the display is disabled.
Video Timing Control Area (this uses the VGA/NTSC Timing Core, the registers are offset by 32)
32 ---- nnnnnnnnnnnn horizontal border begin  
33 ---- nnnnnnnnnnnn horizontal border end  
34 ---- nnnnnnnnnnnn horizontal fetch begin controls when memory fetches  begin
35 ---- nnnnnnnnnnnn horizontal fetch end  
36 ---- nnnnnnnnnnnn vertical border begin  
37 ---- nnnnnnnnnnnn vertical border end  
38 ---- nnnnnnnnnnnn vertical fetch begin  
39 ---- nnnnnnnnnnnn vertical fetch end  
41 -------- LLLLLLLL timing lock register this register controls locking of the critical timing values (sync, blanking and total) so that they can't be changed. By default the timing controls are locked. Writing this register with the value 55 hex will unlock the timing registers. Writing with another value will lock the registers again.
48 ---- nnnnnnnnnnnn horizontal total total number of clock cycles in a horizontal scan line
49 ---- nnnnnnnnnnnn horizontal sync width clock cycle at which horizontal sync ends
50 ---- nnnnnnnnnnnn horizontal blank begin  
51 ---- nnnnnnnnnnnn horizontal blank end  
52 -------- ----nnnn vertical total total number of vertical scan lines including blanking and sync, 0-15 = 1-16 scan lines
53 ---- nnnnnnnnnnnn vertical sync width  
54 ---- nnnnnnnnnnnn vertical blank begin  
55 ---- nnnnnnnnnnnn vertical blank end  
56 -------- -----v-h horizontal and vertical sync polarization levels

h - horizontal polarization level 0 = negative going, 1 = positive going

v - vertical sync polarization level (0= negative going, 1 = positive going)

40,42 - 47 reserved    
57 - 63 reserved    
Color Palette Area
64 - 79 ---------- rrggbb color palette registers these registers control the colors displayed when the color depth is less than five bits per pixel
80 - 95 reserved    
Sprite Control Registers
96 ---- nnnnnnnnnnnn sprite 0 horizontal position  
97 ---- nnnnnnnnnnnn sprite 0 vertical position  
98 Y X A --------- cccccc sprite 0 transparent color code; and sprite horizontal and vertical expansion, alpha blending flag specifies which one of the sprite's colors is transparent; X indicates to double the width of the sprites pixels horizontally, Y performs the same function for the vertical pixels.
99 --hhhhhh --wwwwww sprite 0 width and height control

h - specifies the height of the sprite, must range between 1 and 63

w - specifies the width of the sprite, must range between 1 and 63

The product of h x w must be less than 512.

100-127     These registers control sprites 1 to 7 in the same manner as sprite 0