bus_arb - SoC Bus Arbitrator Core

2004 Bird Computer


    This circuit can be used to arbitrate an SoC bus between up to five requesters. It decides who gets to use the
bus on a bus-cycle by bus-cycle basis. The arbitration mechanism is a simple priority encoder. This style of arbitration should be sufficient for most systems. Arbitration takes place as long as there are requesters. If there are no requesters, then the arbitrator either holds at the last granted requester, or grants to no requesters (depending on the core hold parameter). This core only supports five requesters. Most systems do not need to arbitrate between a lot of different bus
masters. The core is easily extended to support more requesters.

Sample Use
Priority (0 = highest)
0 disk dma
1 video dma
2 audio dma
3 cpu
4 extra

All signals are active high unless otherwise noted.

Download - bus_arb.v


Performance values are approximate (Spartan 2e-6):

6 slices / 10 LUTs / 300 MHz


module bus_arb(rst, clk, ce, rdy,
req0, req1, req2, req3, req4,
sel0, sel1, sel2, sel3, sel4,
sel0_nxt, sel1_nxt, sel2_nxt, sel3_nxt, sel4_nxt);
pHoldBus = 1;

Signal Description
rst This signal is normally connected to the system reset signal. It resets the arbitrator

rst is sampled on the positive edge of the clock

clk this is usually connected to the system clock and is used as a base timing clock.
ce This is a system clock enable. In combination with rdy controls when the arbitrator re-arbitrates.
rdy this input indicates that the current bus cycle is ready to proceed. (Advances the arbitrator).
req0..4 These request inputs notify the arbitrator of devices requesting bus access. The request signal must be asserted before the rising edge of the clock for the bus cycle in which access is desired.
sel0..4 These output signals indicate which device has been granted access for the current bus cycle.
sel?_nxt These signals indicate which device will be granted access during the next bus cycle. (Typically these signals are not used).
pHoldBus This parameter controls whether or not the bus arbitrator holds onto (continues to grant to) the last requester when no request signals are active.