/* ============================================================================
	(C) 2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca

	fifo16s.v
		Small fifo module


    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.


	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.

    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.


    Notes:

   	Verilog 1995
   	Ref: Webpack9.1i xc3s1000-4ft256
	10 slices / 19 LUTs / 132.345 MHz
============================================================================ */

module fifo16s(rst, clk, ce, wr, rd, din, dout, ctr, full, empty);
	parameter WID = 8;
	input rst;			// reset
	input clk;			// clock
	input ce;			// clock enable
	input wr;			// write
	input rd;			// read
	input [WID-1:0] din;	// data input
	output [WID-1:0] dout;	// data output
	output [3:0] ctr;		// queue counter

	output full;
	output empty;

	assign empty = ctr==4'd0;
	wire rdok = ce & rd & ~empty;
	wire wrok = ce & wr & ~full;

	vtdl #(WID) u1 (
		.clk(clk),
		.ce(wrok),
		.a(ctr),
		.d(din),
		.q(dout)
	);

	updown_counter #(4) u2 (
		.rst(rst),
		.clk(clk),
		.ce(ce),
		.inc(wrok),
		.dec(rdok),
		.ld(1'b0),
		.tgt(4'd15),
		.d(4'd0),
		.q(ctr),
		.tc(full)
	);

endmodule