/* ============================================================================
	(C) 2007  Robert T Finch
	All rights reserved.
	rob@birdcomputer.ca

	vtdl - variable tap delay line
		(dynamic shift register)


    This source code is available for evaluation and validation purposes
    only. This copyright statement and disclaimer must remain present in
    the file.


	NO WARRANTY.
    THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
    EXPRESS OR IMPLIED. The user must assume the entire risk of using the
    Work.

    IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
    INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
    THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.

    IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
    IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
    REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
    LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
    AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
    LOSSES RELATING TO SUCH UNAUTHORIZED USE.


    Notes:

	This module acts like a delay line with a variable tap.
	Miscellaneous usage in rate control circuitry such as fifo's.
	Capable of delaying a signal bus.
	Signal bus width is specified with the WID parameter.

   	Verilog 1995
   	Ref: Webpack9.1i xc3s1000-4ft256
	4 slices / 8 LUTs / < 10ns
============================================================================ */

module vtdl(clk, ce, a, d, q);
	parameter WID = 8;
	input clk;
	input ce;
	input [3:0] a;
	input [WID-1:0] d;
	output [WID-1:0] q;

	reg [WID-1:0] m [15:0];
	integer n;

	always @(posedge clk)
		if (ce) begin
			for (n = 1; n < 16; n = n + 1)
				m[n] <= m[n-1];
			m[0] <= d;
		end

	assign q = m[a];

endmodule