rand - 32 bit Random Number Generator Core

2004 Bird Computer


Overview

    This little peripheral uses a 52 bit LFSR (linear feedback shift register) to generate random numbers. Only the lower 32 bits of the LFSR are seedable allowing 2^32 different start values; this also prevents a lockup value from being written to the LFSR. The value register is organized to take up two successive 16 bit memory locations (or one single 32 bit word if a 32 bit bus is selected) so that a word (32 bit) read or write may be performed. The random number shouldn't be read more often than every 32 clock cycles to prevent the appearance of interrelated values. (The values shift over one bit every clock cycle so the same bits are present for 32 clock cycles). However if you just need X bits, the register can be read every X clock cycles.

Use:
To obtain a value write a zero into the command register (reg. #2) then read back the value from the value registers
Note: a new value will appear in the value register only after the command register is written.
To stop the LFSR write a one to the command register
To seed the generator, write the valueLo register, then the valueHi register.

 

All signals are active high unless otherwise noted.

Download - rand.v

 

Performance values are approximate (Spartan 2e-6):

Speed: 150MHz / 63 slices / 108 LUTs


rand

module rand(rst, clk, ce, cs, rdy, wr, addr, din, dout);
parameter
DBW = 16;

Signal Description
rst This signal is normally connected to the system reset signal. It resets the generator

rst is sampled on the positive edge of the clock

clk this is usually connected to the system clock and is used as a base timing clock to shift the LFSR.
ce This is a system clock enable. Data will be latched into the generator on the rising edge of clk when ce is high. This signal may be tied high in systems where data is transfered from the system in a single clock cycle.
cs circuit select - this is how the core identifies a valid bus transfer to / from this circuit.
wr This signal is used to signify a write operation to the generator.
addr This is a two bit address vector used to address one of three available registers. (Registers are described below).
din This is the sixteen or thiry-two bit (selectable via parameter) data input bus to the keyboard interface.
dout This is the sixteen or thirty-two bit data output bus from the keyboard interface.
Parameters  
DBW This parameter controls the width of the bus interface. When thirty-two bits are used, the valueHi register is not used.

Register Description

Reg. No. Function Description
0 value low This register contains the low order sixteen bits of the random number value. A read cycle will read the value, a write cycle will set the low order sixteen bits of the value. If a thirty-two bit bus is specified, then all thirty-two bits of the value are available.
1 value high This register contains the high order sixteen bits of the random number value. A read cycle will read the value, a write cycle will set the high order sixteen bits of the value. If a thirty-two bit bus is specified, then this register is unused.
2 command register bit 0 = 1 = stop / 1 = start generator. The start / stop control bit can be used to prevent the LFSR from cycling.

Any write to the command register causes a snapshot of the LFSR to be taken and transferred to the value register.

3 reserved This register is not used and is reserved.