RTF65002 Processor Project Page

The RTF65002 is a 32 bit processor with an instruction set influenced by the 6502 instruction set. It is a 16 register 32 bit word oriented design. The RTF65002 includes 65C02 and 65C816 emulation modes allowing it to run existing code. In native 32 bit mode the opcodes are redefined in a fashion suitable for 32 bit mode. An attempt has been made to follow the same pattern as the 6502 for opcodes. For instance opcode 69h is an add instruction on the 6502; it's an add instruction on the RTF65002 as well.

Opcode Map – 32 bit mode

 

-0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-A

-B

-C

-D

-E

-F

0-

BRK

OR (d,r)

RR

~

TSB d,r

OR #i8

ASL r,r

OR #i4

PHP

OR #i32

ASL acc

PUSH r

TSB abs

OR abs

ASL abs

~

1-

BPL disp

OR (d),r

OR (r)

~

TRB d,r

OR d,r

ASL d,r

OR r

CLC

OR #i16

INA

TAS

TRB abs

OR abs,r

ASL abs,r

~

2-

JSR abs16

AND (d,r)

JSL abs

~

~

AND #i8

ROL r,r

AND #i4

PLP

AND #i32

ROL acc

POP r

~

AND abs

ROL abs

~

3-

BMI disp

AND (d),r

AND (r)

~

~

AND d,r

ROL d,r

AND r

SEC

AND #i16

DEA

TSA

~

AND abs,r

ROL abs,r

~

4-

RTI

EOR (d,r)

WDM

~

~

EOR #i8

LSR r,r

EOR #i4

PHA

EOR #i32

LSR acc

~

JMP abs16

EOR abs

LSR abs

~

5-

BVC disp

EOR (d),r

EOR (r)

~

~

EOR d,r

LSR d,r

EOR r

CLI

EOR #i16

PHY

~

JML abs

EOR abs,r

LSR abs,r

~

6-

RTS

ADD (d,r)

BSR

~

~

ADD #i8

ROR r,r

ADD #i4

PLA

ADD #i32

ROR acc

~

JMP (abs)

ADD abs

ROR abs

~

7-

BVS disp

ADD (d),r

ADD (r)

~

SB d,r

ADD d,r

ROR d,r

ADD r

SEI

ADD #i16

PLY

~

JMP (abs,x)

ADD abs,r

ROR abs,r

~

8-

BRA disp

ST (d,r)

BRL disp

~

~

~

~

~

DEY

~

TXA

TRS

STY abs

ST abs

STX abs

~

9-

BCC disp

ST (d),r

ST (r)

~

STY d,r

ST d,r

STX d,r

~

TYA

~

TXS

TXY

SB abs

ST abs,r

SB abs,r

~

A-

LDY #i32

ORB (d,r)

LDX #i32

~

~

LDA #i8

LDX #i8

~

TAY

LDA #i32

TAX

TSR

LDY abs

ORB abs

LDX abs

~

B-

BCS disp

ORB (d),r

LDX #i16

~

LDY d,r

ORB d,r

LDX d,r

~

CLV

LDA #i16

TSX

TYX

LDY abs,r

ORB abs,r

LDX abs,r

~

C-

CPY #i32

~

jsr(r)

~

CPY d,r

~

~

~

INY

~

DEX

WAI

CPY abs

~

DEC abs

~

D-

BNE disp

~

jmp(r)

~

~

~

DEC d,r

~

CLD

~

PHX

STP

~

~

DEC abs,r

~

E-

CPX #i32

SUB (d,r)

~

~

CPX d,r

SUB #i8

~

SUB #i4

INX

SUB #i32

NOP

~

CPX abs

SUB abs

INC abs

~

F-

BEQ disp

SUB (d),r

SUB(r)

~

~

SUB d,r

INC d,r

SUB r

SED

SUB #i16

PLX

XCE

JSR (abs,x)

SUB abs,r

INC abs,r

~

 

Opcode Map – 8 bit mode W65C02 compatible

 

= Enhanced instructions not found on the 65C02

 

 

-0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-A

-B

-C

-D

-E

-F

0-

BRK

ORA (d,x)

~

~

TSB d

ORA d

ASL d

~

PHP

OR #i8

ASL acc

~

TSB abs

ORA abs

ASL abs

~

1-

BPL disp

ORA (d),y

ORA (d)

~

TRB d

OR d,x

ASL d,x

~

CLC

OR abs,y

INA

TAS

TRB abs

ORA abs,x

ASL abs,x

~

2-

JSR abs

AND (d,x)

JSL abs24

~

BIT d

AND d

ROL d

~

PLP

AND #i8

ROL acc

~

BIT abs

AND abs

ROL abs

~

3-

BMI disp

AND (d),y

AND (d)

~

BIT d,x

AND d,x

ROL d,x

~

SEC

AND abs,y

DEA

TSA

BIT abs,x

AND abs,x

ROL abs,x

~

4-

RTI

EOR (d,x)

~

~

~

EOR d

LSR d

~

PHA

EOR #i8

LSR acc

~

JMP abs

EOR abs

LSR abs

~

5-

BVC disp

EOR (d),y

EOR (d)

~

~

EOR d,x

LSR d,x

~

CLI

EOR abs,y

PHY

~

JML abs24

EOR abs,x

LSR abs,x

~

6-

RTS

ADC (d,x)

~

~

STZ d

ADC d

ROR d

~

PLA

ADC #i8

ROR acc

RTL

JMP (abs)

ADC abs

ROR abs

~

7-

BVS disp

ADC (d),y

ADC (d)

~

STZ d,x

ADC d,x

ROR d,x

~

SEI

ADC abs,y

PLY

~

JMP (abs,x)

ADC abs,x

ROR abs,x

~

8-

BRA disp

STA (d,x)

BRL disp

~

STY d

STA d

STX d

~

DEY

BIT #

TXA

~

STY abs

STA abs

STX abs

~

9-

BCC disp

STA (d),y

STA (d)

~

STY d,x

STA d,x

STX d,y

~

TYA

STA abs,y

TXS

TXY

STZ abs

STA abs,x

STZ abs,x

~

A-

LDY #i8

LDA (d,x)

~

~

LDY d

LDA d

LDX #i8

~

TAY

LDA #i8

TAX

~

LDY abs

LDA abs

LDX abs

~

B-

BCS disp

LDA (d),y

LDA (d)

~

LDY d,x

LDA d,x

LDX d,y

~

CLV

LDA abs,y

TSX

TYX

LDY abs,x

LDA abs,x

LDX abs,x

~

C-

CPY #i8

CMP (d,x)

~

~

CPY d

CMP d

DEC d

~

INY

CMP #i8

DEX

WAI

CPY abs

CMP abs

DEC abs

~

D-

BNE disp

CMP (d),y

CMP (d)

~

~

CMP d,x

DEC d,r

~

CLD

CMP abs,y

PHX

STP

~

CMP abs,x

DEC abs,x

~

E-

CPX #i8

SBC(d,x)

~

~

CPX d

SUB d

INC d

~

INX

SBC #i8

NOP

~

CPX abs

SBC abs

INC abs

~

F-

BEQ disp

SBC (d),y

SBC(r)

~

~

SUB d,x

INC d,r

~

SED

SBC abs,y

PLX

XCE

JSR (abs,x)

SBC abs,x

INC abs,x

~

 

Addressing modes:

Mode   Clock Cycles  

Rn

Register direct

2

 

#imm4

Four bit sign extended immediate 2  

#imm8

Eight bit sign extended immediate

2

 

#imm16

Sixteen bit sign extended immediate

2

 

#imm32

Thirty-two bit immediate

2

 

zp,Rb

Zero page indexed

4

 

(zp,Rb)

Zero page indexed indirect (inner indexed)

5

 

(zp),Rb

Zero page indirect indexed (outer indexed)

6

 

abs

absolute

4

 

abs,Rb

Absolute indexed

4

 

(Rb)

Register indirect

4

label

Relative branch

2

 

 

 In 32 bit mode all zero page access is indexed by a register. Non-indexed zero page addresses are generated by specifying R0 as the index register. Zero page addresses have been extended to 12 bits, which provides for up to 4kW of zero page space.

There are three forms of immediate instructions (8,16, or 32 bit) for most operations on the RTF65002. The 6502 only requires a single immediate format since all the registers are only eight bits wide. Being 32 bits, RTF65002 uses three forms in order to conserve code space. Many constants are small and constants represent up to about 1/3 of the code executed. So it makes some sense to accomodate them as efficiently as possible. The additional immediate forms are accomodated using up some of the redundant opcode space that results from its 6502 basis.

For the 65002 any of 16 registers can be used as an index register, the index register spec is part of additional opcode bytes for the instruction. Hence there is only one format for indexed register operations. The 6502 has separate instruction for both the X and Y index registers; on the RTF65002 there is only a single opcode required to indicate indexed mode. The redundant opcodes from the 6502 opcode map have been reused to support additional immediate addressing modes.

Also in 32 bit mode some instructions of the 6502 would be redundant. For instance CMP is just a SUB with the target register set to R0. This means there is no point to having a separate CMP instruction in 32 bit mode. The RTF65002 assembler handles alternate mnemonics for instructions so that the instruction set looks like the familiar 6502 instruction set. The assembler will accept CMP R1,#12324 as an instruction and convert it to SUB R0,R1,#12324 automatically.

Short forms for instructions:

The accumulator is defined to be register R1, the X index register is defined to be register R2, and Y is defined to be R3. There are shorter forms of instructions for operations dealing with the A, X, and Y registers. For instance the PUSH instruction can push any register on the stack, but it takes two bytes. Short form instructions for pushing the accumulator, X and Y registers are PHA, PHX, and PHY which take only a single byte. As a second example, it is possible to add an immediate value to any register eg ADD R2,R2,#1 will add one to the X register, however it's a three byte instruction to do so. The INX instruction does the same thing while consuming only a single byte of code.

Memory Addressing

Memory addresses for data are 32 bit word addresses. Memory access in 32 bit mode only allows access to whole words.  For example LD r1,$1 loads the word from word address $1 (which would be byte address $4). Note that program code is byte addressable, while data objects are only word addressable.

Operands

The RTF65002 follows a RISC paradigm of instruction triples. There are three operands for most instructions, these being a target register, an operand 'A' register, and a third operand 'B' which may be either a register or a memory operand.

The assembler can process implied operands for many instructions. For instance ADD #123 implies an addition of #123 to the accumulator register. This really assembles as the generic ADD r1,r1,#123 instruction. If one examines the assembled code, one finds the RISC triples in object code, even though the instruction may have been specified with only a singe operand.

Registers

General Registers

 

 

 

Usage

R0

z

This register is always zero

 

R1

acc

Accumulator

First parameter / return value

R2

x

‘x’ index register

Second parameter

R3

y

‘y’ index register

Third parameter

R4

 

 

 

R5

 

 

 

R6

 

 

 

R7

 

 

 

R8

 

 

 

R9

 

 

 

R10

 

 

 

R11

 

 

 

R12

 

 

 

R13

 

 

 

R14

 

 

 

R15

 

 

 

 

 

 

 

 

Special Purpose Registers

Code

 

 

 

0

cc

Cache control register

 

1

dp

Direct page register

 

…

 

 

 

14

sp8

8/16 bit mode stack pointer

 

15

sp

Native mode Stack pointer

 

 

 

 

 

 

Instruction Set

Clock cycle timings are assuming cache hits for both instructions and data.

ADD

Flags: v c n z

Bytes

Cyc

Byte 7

Byte 6

Byte5

Byte 4

Byte 3

Byte 2

Byte 1

 

 

 
    Ra Rt 77h ADD Rt,Ra

2

2
    Imm4

Rt

67h

ADD Rt,#imm4

2

2

 

0

Rt

Rb

Ra

02h

ADD Rt,Ra,Rb

3

2

 

Imm8

Rt

Ra

65h

ADD Rt,Ra,#imm8

3

2

 

Imm16

Rt

Ra

79h

ADD Rt,Ra,#imm16

4

2

 

Imm32

Rt

Ra

69h

ADD Rt,Ra,#imm32

6

2

 

Addr12

Rt

Rb

Ra

75h

ADD Rt,Ra,zp,Rb

4

4

 

Addr12

Rt

Rb

Ra

61h

ADD Rt,Ra,(zp,Rb)

4

5

 

Addr12

Rt

Rb

Ra

71h

ADD Rt,Ra,(zp),Rb

4

6

 

Addr32

Rt

Ra

6Dh

ADD Rt,Ra,abs

6

4

Addr32

~4

Rt

Rb

Ra

7Dh

ADD Rt,Ra,abs,Rb

7

4

 

~4

Rt

Rb

Ra

72h

ADD Rt,Ra,(Rb)

3

4

 

SUB

Flags: v c n z

Bytes

Ra Rt F7h SUB Rt,Ra 2
        Imm4 Rt E7h SUB Rt,#imm4 2

 

 

1

Rt

Rb

Ra

02h

SUB Rt,Ra,Rb

3

 

 

 

Imm8

Rt

Ra

E5h

SUB Rt,Ra,#imm8

3

 

 

Imm16

Rt

Ra

F9h

SUB Rt,Ra,#imm16

4

 

Imm32

Rt

Ra

E9h

SUB Rt,Ra,#imm32

6

 

 

Addr12

Rt

Rb

Ra

F5h

SUB Rt,Ra,zp,Rb

4

 

 

Addr12

Rt

Rb

Ra

E1h

SUB Rt,Ra, (zp,Rb)

4

 

 

Addr12

Rt

Rb

Ra

F1h

SUB Rt,Ra, (zp),Rb

4

 

Addr32

Rt

Ra

EDh

SUB Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

FDh

SUB Rt,Ra,abs,Rb

7

 

~4

Rt

Rb

Ra

F2h

SUB Rt,Ra, (Rb)

3

 

CMP

Flags: c n z

Bytes

 

 

1

0

Rb

Ra

02h

CMP Ra,Rb

3

 

 

 

Imm8

0

Ra

E5h

CMP Ra,#imm8

3

 

 

Imm16

0

Ra

F9h

CMP Ra,#imm16

4

 

Imm32

0

Ra

E9h

CMP Ra,#imm32

6

 

 

Addr12

0

Rb

Ra

F5h

CMP Ra,zp,Rb

4

 

 

Addr12

0

Rb

Ra

E1h

CMP Ra, (zp,Rb)

4

 

 

Addr12

0

Rb

Ra

F1h

CMP Ra, (zp),Rb

4

 

Addr32

0

Ra

EDh

CMP Ra,abs

6

Addr32

 

0

Rb

Ra

FDh

CMP Ra,abs,Rb

7

 

~4

0

Rb

Ra

F2h

CMP Ra, (Rb)

3

CMP is an alternate mnemonic for SUB where the target register is R0. CMP does not affect the overflow flag.

 

AND

Flags: n z

Bytes

        Ra Rt 37h AND Rt,Ra 2
        Imm4 Rt 27h AND Rt,#imm4 2

 

 

3

Rt

Rb

Ra

02h

AND Rt,Ra,Rb

3

 

 

 

Imm8

Rt

Ra

25h

AND Rt,Ra,#imm8

3

 

 

Imm16

Rt

Ra

39h

AND Rt,Ra,#imm16

4

 

Imm32

Rt

Ra

29h

AND Rt,Ra,#imm32

6

 

 

Addr12

Rt

Rb

Ra

35h

AND Rt,Ra,zp,Rb

4

 

 

Addr12

Rt

Rb

Ra

21h

AND Rt,Ra, (zp,Rb)

4

 

 

Addr12

Rt

Rb

Ra

31h

AND Rt,Ra, (zp),Rb

4

 

Addr32

Rt

Ra

2Dh

AND Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

3Dh

AND Rt,Ra,abs,Rb

7

 

~4

Rt

Rb

Ra

32h

AND Rt,Ra, (Rb)

3

 

OR

Flags: n z

Bytes

 

 

5

Rt

Rb

Ra

02h

OR Rt,Ra,Rb

3

 

 

 

Imm8

Rt

Ra

05h

OR Rt,Ra,#imm8

3

 

 

Imm16

Rt

Ra

19h

OR Rt,Ra,#imm16

4

 

Imm32

Rt

Ra

09h

OR Rt,Ra,#imm32

6

 

 

Addr12

Rt

Rb

Ra

15h

OR Rt,Ra,zp,Rb

4

 

 

Addr12

Rt

Rb

Ra

01h

OR Rt,Ra, (zp,Rb)

4

 

 

Addr12

Rt

Rb

Ra

11h

OR Rt,Ra, (zp),Rb

4

 

Addr32

Rt

Ra

0Dh

OR Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

1Dh

OR Rt,Ra,abs,Rb

7

 

~4

Rt

Rb

Ra

12h

OR Rt,Ra, (Rb)

3

 

ORB

Flags: n z

Bytes

 

 

Addr12

Rt

Rb

Ra

B5h

OR Rt,Ra,zp,Rb

4

 

Addr32

Rt

Ra

ADh

OR Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

BDh

OR Rt,Ra,abs,Rb

7

The ORB instruction loads a byte from memory and zero extends it before performing an a OR operation. The address fields represent a byte address.

 

EOR

Flags: n z

Bytes

 

 

4

Rt

Rb

Ra

02h

EOR Rt,Ra,Rb

3

 

 

 

Imm8

Rt

Ra

45h

EOR Rt,Ra,#imm8

3

 

 

Imm16

Rt

Ra

59h

EOR Rt,Ra,#imm16

4

 

Imm32

Rt

Ra

49h

EOR Rt,Ra,#imm32

6

 

 

Addr12

Rt

Rb

Ra

55h

EOR Rt,Ra,zp,Rb

4

 

 

Addr12

Rt

Rb

Ra

41h

EOR Rt,Ra, (zp,Rb)

4

 

 

Addr12

Rt

Rb

Ra

51h

EOR Rt,Ra, (zp),Rb

4

 

Addr32

Rt

Ra

4Dh

EOR Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

5Dh

EOR Rt,Ra,abs,Rb

7

 

~4

Rt

Rb

Ra

52h

EOR Rt,Ra, (Rb)

3

 

BIT

Flags: v n z

Bytes

 

-          Bit is the AND operation with no target register; the overflow status is set to bit 30 of the result

 

 

 

3

0

Rb

Ra

02h

BIT Ra,Rb

3

 

 

 

Imm8

0

Ra

25h

BIT Ra,#imm8

3

 

 

Imm16

0

Ra

39h

BIT Ra,#imm16

4

 

Imm32

0

Ra

29h

BIT Ra,#imm32

6

 

 

Addr12

0

Rb

Ra

35h

BIT Ra,zp,Rb

4

 

 

Addr12

0

Rb

Ra

21h

BIT Ra, (zp,Rb)

4

 

 

Addr12

0

Rb

Ra

31h

BIT Ra, (zp),Rb

4

 

Addr32

0

Ra

2Dh

BIT Ra,abs

6

Addr32

 

0

Rb

Ra

3Dh

BIT Ra,abs,Rb

7

 

~4

0

Rb

Ra

32h

BIT Ra, (Rb)

3

 

Load and Store Instructions

Arithmetic and logical instructions can take a memory operand as the third operand of the instruction. This effectively turns all these instructions into load instructions. Hence there isn’t an explicit load instruction. The OR or EOR instructions can readily be used to perform a load operation.

Because addresses are word addresses, the address field in the instructions is normally shifted left twice resulting in a 34 bit data address. The only exception to this is the byte load and store instructions.

 

LD

Flags: n z

Bytes

 

 

 

Imm8

Rt

0

05h

LD Rt,#imm8

3

 

 

Imm16

Rt

0

19h

LD Rt,#imm16

4

 

Imm32

Rt

0

09h

LD Rt,#imm32

6

 

 

Addr12

Rt

Rb

0

15h

LD Rt,zp,Rb

4

 

 

Addr12

Rt

Rb

0

01h

LD Rt, (zp,Rb)

4

 

 

Addr12

Rt

Rb

0

11h

LD Rt, (zp),Rb

4

 

Addr32

Rt

0

0Dh

LD Rt,abs

6

Addr32

 

Rt

Rb

0

1Dh

LD Rt,abs,Rb

7

 

~4

Rt

Rb

0

12h

LD Rt, (Rb)

3

LD is an alternate mnemonic for the OR instruction where register Ra is zero.

LB

Flags: n z

Bytes

 

 

Addr12

Rt

Rb

Ra

B5h

LB Rt,Ra,zp,Rb

4

 

Addr32

Rt

Ra

ADh

LB Rt,Ra,abs

6

Addr32

 

Rt

Rb

Ra

BDh

LB Rt,Ra,abs,Rb

7

LB is an alternate mnemonic for the ORB instruction where register Ra is zero.

LDA

Flags: n z

Bytes

 

 

 

Imm8

1

0

05h

LD Rt,#imm8

3

 

 

Imm16

1

0

19h

LD Rt,#imm16

4

 

Imm32

1

0

09h

LD Rt,#imm32

6

 

 

Addr12

1

Rb

0

15h

LD Rt,zp,Rb

4

 

 

Addr12

1

Rb

0

01h

LD Rt, (zp,Rb)

4

 

 

Addr12

1

Rb

0

11h

LD Rt, (zp),Rb

4

 

Addr32

Rt

0

0Dh

LD Rt,abs

6

Addr32

 

1

Rb

0

1Dh

LD Rt,abs,Rb

7

 

~4

1

Rb

0

12h

LD Rt, (Rb)

3

LDA is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is one.

LDX

Flags: n z

Bytes

 

 

 

Imm8

2

0

05h

LDX #imm8

3

 

 

Imm16

2

0

19h

LDX #imm16

4

 

Imm32

2

0

09h

LDX #imm32

6

 

 

Addr12

2

Rb

0

15h

LDX zp,Rb

4

 

 

Addr12

2

Rb

0

01h

LDX (zp,Rb)

4

 

 

Addr12

2

Rb

0

11h

LDX (zp),Rb

4

 

Addr32

Rt

0

0Dh

LDX abs

6

Addr32

 

2

Rb

0

1Dh

LDX abs,Rb

7

 

~4

2

Rb

0

12h

LDX (Rb)

3

LDX is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is two.

 

LDY

Flags: n z

Bytes

 

 

 

Imm8

3

0

05h

LDY #imm8

3

 

 

Imm16

3

0

19h

LDY #imm16

4

 

Imm32

3

0

09h

LDY #imm32

6

 

 

Addr12

3

Rb

0

15h

LDY zp,Rb

4

 

 

Addr12

3

Rb

0

01h

LDY (zp,Rb)

4

 

 

Addr12

3

Rb

0

11h

LDY (zp),Rb

4

 

Addr32

Rt

0

0Dh

LDY abs

6

Addr32

 

3

Rb

0

1Dh

LDY abs,Rb

7

 

~4

3

Rb

0

12h

LDY (Rb)

3

LDY is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is three.

 

ST

Flags: none

Bytes

 

 

Addr12

0

Rb

Ra

95h

ST Ra,zp,Rb

4

 

 

Addr12

0

Rb

Ra

81h

ST Ra, (zp,Rb)

4

 

 

Addr12

0

Rb

Ra

91h

ST Ra, (zp),Rb

4

 

Addr32

0

Ra

8Dh

ST Ra,abs

6

Addr32

 

0

Rb

Ra

9Dh

ST Ra,abs,Rb

7

 

~4

Rt

Rb

Ra

92h

ST Ra, (Rb)

3

 

SB

Flags: none

Bytes

 

 

Addr12

0

Rb

Ra

74h

SB Ra,zp,Rb

4

 

Addr32

0

Ra

9Ch

SB Ra,abs

6

Addr32

 

0

Rb

Ra

9Eh

SB Ra,abs,Rb

7

 

STA

Flags: none

Bytes

 

 

Addr12

0

Rb

1

95h

STA zp,Rb

4

 

 

Addr12

0

Rb

1

81h

STA (zp,Rb)

4

 

 

Addr12

0

Rb

1

91h

STA (zp),Rb

4

 

Addr32

0

1

8Dh

STA abs

6

Addr32

 

0

Rb

1

9Dh

STA abs,Rb

7

 

~4

Rt

Rb

1

92h

STA (Rb)

3

STA is an alternate mnemonic for ST where the register to be stored is R1 (the accumulator).

STX

Flags: none

Bytes

 

 

Addr12

0

Rb

2

95h

STX zp,Rb

4

 

 

Addr12

0

Rb

2

81h

STX (zp,Rb)

4

 

 

Addr12

0

Rb

2

91h

STX (zp),Rb

4

 

Addr32

0

2

8Dh

STX abs

6

Addr32

 

0

Rb

2

9Dh

STX abs,Rb

7

 

~4

Rt

Rb

2

92h

STX (Rb)

3

STX is an alternate mnemonic for ST where the register to be stored is R2 (the x index register). There are also additional short-hand forms for the STX instruction.

STY

Flags: none

Bytes

 

 

Addr12

0

Rb

3

95h

STY zp,Rb

4

 

 

Addr12

0

Rb

3

81h

STY (zp,Rb)

4

 

 

Addr12

0

Rb

3

91h

STY (zp),Rb

4

 

Addr32

0

3

8Dh

STY abs

6

Addr32

 

0

Rb

3

9Dh

STY abs,Rb

7

 

~4

Rt

Rb

3

92h

STY (Rb)

3

STY is an alternate mnemonic for ST where the register to be stored is R3 (the y index register). There are also additional short-hand forms for the STY instruction.

 

Shift Operations / Read-modify-write memory operations.

ASL

Flags: c n z

Bytes

 

 

 

 

 

0Ah

ASL acc

1

 

 

 

Rt

Ra

06h

ASL Rt,Ra

2

 

 

 

Addr12

Rb

16h

ASL zp,Rb

3

 

 

Addr32

0Eh

ASL abs

5

 

Addr32

Rb

0

1Eh

ASL abs,Rb

6

 

ROL

Flags: c n z

Bytes

 

 

 

 

 

2Ah

ROL acc

1

 

 

 

Rt

Ra

26h

ROL Rt,Ra

2

 

 

 

Addr12

Rb

36h

ROL zp,Rb

3

 

 

Addr32

2Eh

ROL abs

5

 

Addr32

Rb

0

3Eh

ROL abs,Rb

6

 

LSR

Flags: c n z

Bytes

 

 

 

 

 

4Ah

LSR acc

1

 

 

 

Rt

Ra

46h

LSR Rt,Ra

2

 

 

 

Addr12

Rb

56h

LSR zp,Rb

3

 

 

Addr32

4Eh

LSR abs

5

 

Addr32

Rb

0

5Eh

LSR abs,Rb

6

 

ROR

Flags: c n z

Bytes