RTF65002 Processor Project Page

The RTF65002 is a 32 bit processor with an instruction set influenced by the 6502 instruction set. It is a 16 register 32 bit word oriented design. The RTF65002 includes 65C02 and 65C816 emulation modes allowing it to run existing code. In native 32 bit mode the opcodes are redefined in a fashion suitable for 32 bit mode. An attempt has been made to follow the same pattern as the 6502 for opcodes. For instance opcode 69h is an add instruction on the 6502; it's an add instruction on the RTF65002 as well.

Opcode Map – 32 bit mode

-0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-A

-B

-C

-D

-E

-F

BRK

OR (d,r)

TSB d,r

OR #i8

ASL r,r

OR #i4

PHP

OR #i32

ASL acc

PUSH r

TSB abs

OR abs

ASL abs

BPL disp

OR (d),r

OR (r)

TRB d,r

OR d,r

ASL d,r

OR r

CLC

OR #i16

INA

TAS

TRB abs

OR abs,r

ASL abs,r

JSR abs16

AND (d,r)

JSL abs

AND #i8

ROL r,r

AND #i4

PLP

AND #i32

ROL acc

POP r

AND abs

ROL abs

BMI disp

AND (d),r

AND (r)

AND d,r

ROL d,r

AND r

SEC

AND #i16

DEA

TSA

AND abs,r

ROL abs,r

RTI

EOR (d,r)

WDM

EOR #i8

LSR r,r

EOR #i4

PHA

EOR #i32

LSR acc

JMP abs16

EOR abs

LSR abs

BVC disp

EOR (d),r

EOR (r)

EOR d,r

LSR d,r

EOR r

CLI

EOR #i16

PHY

JML abs

EOR abs,r

LSR abs,r

RTS

ADD (d,r)

BSR

ADD #i8

ROR r,r

ADD #i4

PLA

ADD #i32

ROR acc

JMP (abs)

ADD abs

ROR abs

BVS disp

ADD (d),r

ADD (r)

SB d,r

ADD d,r

ROR d,r

ADD r

SEI

ADD #i16

PLY

JMP (abs,x)

ADD abs,r

ROR abs,r

BRA disp

ST (d,r)

BRL disp

DEY

TXA

TRS

STY abs

ST abs

STX abs

BCC disp

ST (d),r

ST (r)

STY d,r

ST d,r

STX d,r

TYA

TXS

TXY

SB abs

ST abs,r

SB abs,r

A-

LDY #i32

ORB (d,r)

LDX #i32

LDA #i8

LDX #i8

TAY

LDA #i32

TAX

TSR

LDY abs

ORB abs

LDX abs

B-

BCS disp

ORB (d),r

LDX #i16

LDY d,r

ORB d,r

LDX d,r

CLV

LDA #i16

TSX

TYX

LDY abs,r

ORB abs,r

LDX abs,r

C-

CPY #i32

jsr(r)

CPY d,r

INY

DEX

WAI

CPY abs

DEC abs

D-

BNE disp

jmp(r)

DEC d,r

CLD

PHX

STP

DEC abs,r

E-

CPX #i32

SUB (d,r)

CPX d,r

SUB #i8

SUB #i4

INX

SUB #i32

NOP

CPX abs

SUB abs

INC abs

F-

BEQ disp

SUB (d),r

SUB(r)

SUB d,r

INC d,r

SUB r

SED

SUB #i16

PLX

XCE

JSR (abs,x)

SUB abs,r

INC abs,r

Opcode Map – 8 bit mode W65C02 compatible

= Enhanced instructions not found on the 65C02

-0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-A

-B

-C

-D

-E

-F

BRK

ORA (d,x)

TSB d

ORA d

ASL d

PHP

OR #i8

ASL acc

TSB abs

ORA abs

ASL abs

BPL disp

ORA (d),y

ORA (d)

TRB d

OR d,x

ASL d,x

CLC

OR abs,y

INA

TAS

TRB abs

ORA abs,x

ASL abs,x

JSR abs

AND (d,x)

JSL abs24

BIT d

AND d

ROL d

PLP

AND #i8

ROL acc

BIT abs

AND abs

ROL abs

BMI disp

AND (d),y

AND (d)

BIT d,x

AND d,x

ROL d,x

SEC

AND abs,y

DEA

TSA

BIT abs,x

AND abs,x

ROL abs,x

RTI

EOR (d,x)

EOR d

LSR d

PHA

EOR #i8

LSR acc

JMP abs

EOR abs

LSR abs

BVC disp

EOR (d),y

EOR (d)

EOR d,x

LSR d,x

CLI

EOR abs,y

PHY

JML abs24

EOR abs,x

LSR abs,x

RTS

ADC (d,x)

STZ d

ADC d

ROR d

PLA

ADC #i8

ROR acc

RTL

JMP (abs)

ADC abs

ROR abs

BVS disp

ADC (d),y

ADC (d)

STZ d,x

ADC d,x

ROR d,x

SEI

ADC abs,y

PLY

JMP (abs,x)

ADC abs,x

ROR abs,x

BRA disp

STA (d,x)

BRL disp

STY d

STA d

STX d

DEY

BIT #

TXA

STY abs

STA abs

STX abs

BCC disp

STA (d),y

STA (d)

STY d,x

STA d,x

STX d,y

TYA

STA abs,y

TXS

TXY

STZ abs

STA abs,x

STZ abs,x

A-

LDY #i8

LDA (d,x)

LDY d

LDA d

LDX #i8

TAY

LDA #i8

TAX

LDY abs

LDA abs

LDX abs

B-

BCS disp

LDA (d),y

LDA (d)

LDY d,x

LDA d,x

LDX d,y

CLV

LDA abs,y

TSX

TYX

LDY abs,x

LDA abs,x

LDX abs,x

C-

CPY #i8

CMP (d,x)

CPY d

CMP d

DEC d

INY

CMP #i8

DEX

WAI

CPY abs

CMP abs

DEC abs

D-

BNE disp

CMP (d),y

CMP (d)

CMP d,x

DEC d,r

CLD

CMP abs,y

PHX

STP

CMP abs,x

DEC abs,x

E-

CPX #i8

SBC(d,x)

CPX d

SUB d

INC d

INX

SBC #i8

NOP

CPX abs

SBC abs

INC abs

F-

BEQ disp

SBC (d),y

SBC(r)

SUB d,x

INC d,r

SED

SBC abs,y

PLX

XCE

JSR (abs,x)

SBC abs,x

INC abs,x

Addressing modes:

Mode		Clock Cycles
Rn	Register direct	2
#imm4	Four bit sign extended immediate	2
#imm8	Eight bit sign extended immediate	2
#imm16	Sixteen bit sign extended immediate	2
#imm32	Thirty-two bit immediate	2
zp,Rb	Zero page indexed	4
(zp,Rb)	Zero page indexed indirect (inner indexed)	5
(zp),Rb	Zero page indirect indexed (outer indexed)	6
abs	absolute	4
abs,Rb	Absolute indexed	4
(Rb)	Register indirect	4
label	Relative branch	2

In 32 bit mode all zero page access is indexed by a register. Non-indexed zero page addresses are generated by specifying R0 as the index register. Zero page addresses have been extended to 12 bits, which provides for up to 4kW of zero page space.

There are three forms of immediate instructions (8,16, or 32 bit) for most operations on the RTF65002. The 6502 only requires a single immediate format since all the registers are only eight bits wide. Being 32 bits, RTF65002 uses three forms in order to conserve code space. Many constants are small and constants represent up to about 1/3 of the code executed. So it makes some sense to accomodate them as efficiently as possible. The additional immediate forms are accomodated using up some of the redundant opcode space that results from its 6502 basis.

For the 65002 any of 16 registers can be used as an index register, the index register spec is part of additional opcode bytes for the instruction. Hence there is only one format for indexed register operations. The 6502 has separate instruction for both the X and Y index registers; on the RTF65002 there is only a single opcode required to indicate indexed mode. The redundant opcodes from the 6502 opcode map have been reused to support additional immediate addressing modes.

Also in 32 bit mode some instructions of the 6502 would be redundant. For instance CMP is just a SUB with the target register set to R0. This means there is no point to having a separate CMP instruction in 32 bit mode. The RTF65002 assembler handles alternate mnemonics for instructions so that the instruction set looks like the familiar 6502 instruction set. The assembler will accept CMP R1,#12324 as an instruction and convert it to SUB R0,R1,#12324 automatically.

Short forms for instructions:

The accumulator is defined to be register R1, the X index register is defined to be register R2, and Y is defined to be R3. There are shorter forms of instructions for operations dealing with the A, X, and Y registers. For instance the PUSH instruction can push any register on the stack, but it takes two bytes. Short form instructions for pushing the accumulator, X and Y registers are PHA, PHX, and PHY which take only a single byte. As a second example, it is possible to add an immediate value to any register eg ADD R2,R2,#1 will add one to the X register, however it's a three byte instruction to do so. The INX instruction does the same thing while consuming only a single byte of code.

Memory Addressing

Memory addresses for data are 32 bit word addresses. Memory access in 32 bit mode only allows access to whole words. For example LD r1,$1 loads the word from word address $1 (which would be byte address $4). Note that program code is byte addressable, while data objects are only word addressable.

Operands

The RTF65002 follows a RISC paradigm of instruction triples. There are three operands for most instructions, these being a target register, an operand 'A' register, and a third operand 'B' which may be either a register or a memory operand.

The assembler can process implied operands for many instructions. For instance ADD #123 implies an addition of #123 to the accumulator register. This really assembles as the generic ADD r1,r1,#123 instruction. If one examines the assembled code, one finds the RISC triples in object code, even though the instruction may have been specified with only a singe operand.

Registers

General Registers

			Usage
R0	z	This register is always zero
R1	acc	Accumulator	First parameter / return value
R2	x	‘x’ index register	Second parameter
R3	y	‘y’ index register	Third parameter
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

Special Purpose Registers

Code
0	cc	Cache control register
1	dp	Direct page register
…
14	sp8	8/16 bit mode stack pointer
15	sp	Native mode Stack pointer

Instruction Set

Clock cycle timings are assuming cache hits for both instructions and data.

ADD

Flags: v c n z

Bytes

Cyc

Byte 7

Byte 6

Byte5

Byte 4

Byte 3

Byte 2

Byte 1

_Ra

77h

ADD Rt,Ra

Imm₄

67h

ADD Rt,#imm4

02h

ADD Rt,Ra,Rb

Imm₈

65h

ADD Rt,Ra,#imm8

Imm₁₆

79h

ADD Rt,Ra,#imm16

Imm₃₂

69h

ADD Rt,Ra,#imm32

Addr₁₂

75h

ADD Rt,Ra,zp,Rb

Addr₁₂

61h

ADD Rt,Ra,(zp,Rb)

Addr₁₂

71h

ADD Rt,Ra,(zp),Rb

Addr₃₂

6Dh

ADD Rt,Ra,abs

Addr₃₂

~₄

7Dh

ADD Rt,Ra,abs,Rb

~₄

72h

ADD Rt,Ra,(Rb)

SUB

Flags: v c n z

Bytes

F7h

SUB Rt,Ra

Imm₄

E7h

SUB Rt,#imm4

02h

SUB Rt,Ra,Rb

Imm₈

E5h

SUB Rt,Ra,#imm8

Imm₁₆

F9h

SUB Rt,Ra,#imm16

Imm₃₂

E9h

SUB Rt,Ra,#imm32

Addr₁₂

F5h

SUB Rt,Ra,zp,Rb

Addr₁₂

E1h

SUB Rt,Ra, (zp,Rb)

Addr₁₂

F1h

SUB Rt,Ra, (zp),Rb

Addr₃₂

EDh

SUB Rt,Ra,abs

Addr₃₂

FDh

SUB Rt,Ra,abs,Rb

~₄

F2h

SUB Rt,Ra, (Rb)

CMP

Flags: c n z

Bytes

02h

CMP Ra,Rb

Imm₈

E5h

CMP Ra,#imm8

Imm₁₆

F9h

CMP Ra,#imm16

Imm₃₂

E9h

CMP Ra,#imm32

Addr₁₂

F5h

CMP Ra,zp,Rb

Addr₁₂

E1h

CMP Ra, (zp,Rb)

Addr₁₂

F1h

CMP Ra, (zp),Rb

Addr₃₂

EDh

CMP Ra,abs

Addr₃₂

FDh

CMP Ra,abs,Rb

~₄

F2h

CMP Ra, (Rb)

CMP is an alternate mnemonic for SUB where the target register is R0. CMP does not affect the overflow flag.

AND

Flags: n z

Bytes

37h

AND Rt,Ra

Imm₄

27h

AND Rt,#imm4

02h

AND Rt,Ra,Rb

Imm₈

25h

AND Rt,Ra,#imm8

Imm₁₆

39h

AND Rt,Ra,#imm16

Imm₃₂

29h

AND Rt,Ra,#imm32

Addr₁₂

35h

AND Rt,Ra,zp,Rb

Addr₁₂

21h

AND Rt,Ra, (zp,Rb)

Addr₁₂

31h

AND Rt,Ra, (zp),Rb

Addr₃₂

2Dh

AND Rt,Ra,abs

Addr₃₂

3Dh

AND Rt,Ra,abs,Rb

~₄

32h

AND Rt,Ra, (Rb)

Flags: n z

Bytes

02h

OR Rt,Ra,Rb

Imm₈

05h

OR Rt,Ra,#imm8

Imm₁₆

19h

OR Rt,Ra,#imm16

Imm₃₂

09h

OR Rt,Ra,#imm32

Addr₁₂

15h

OR Rt,Ra,zp,Rb

Addr₁₂

01h

OR Rt,Ra, (zp,Rb)

Addr₁₂

11h

OR Rt,Ra, (zp),Rb

Addr₃₂

0Dh

OR Rt,Ra,abs

Addr₃₂

1Dh

OR Rt,Ra,abs,Rb

~₄

12h

OR Rt,Ra, (Rb)

ORB	Flags: n z							Bytes
		Addr₁₂	Rt	Rb	Ra	B5h	OR Rt,Ra,zp,Rb	4
	Addr₃₂			Rt	Ra	ADh	OR Rt,Ra,abs	6
Addr₃₂			Rt	Rb	Ra	BDh	OR Rt,Ra,abs,Rb	7

The ORB instruction loads a byte from memory and zero extends it before performing an a OR operation. The address fields represent a byte address.

EOR

Flags: n z

Bytes

02h

EOR Rt,Ra,Rb

Imm₈

45h

EOR Rt,Ra,#imm8

Imm₁₆

59h

EOR Rt,Ra,#imm16

Imm₃₂

49h

EOR Rt,Ra,#imm32

Addr₁₂

55h

EOR Rt,Ra,zp,Rb

Addr₁₂

41h

EOR Rt,Ra, (zp,Rb)

Addr₁₂

51h

EOR Rt,Ra, (zp),Rb

Addr₃₂

4Dh

EOR Rt,Ra,abs

Addr₃₂

5Dh

EOR Rt,Ra,abs,Rb

~₄

52h

EOR Rt,Ra, (Rb)

BIT

Flags: v n z

Bytes

- Bit is the AND operation with no target register; the overflow status is set to bit 30 of the result

02h

BIT Ra,Rb

Imm₈

25h

BIT Ra,#imm8

Imm₁₆

39h

BIT Ra,#imm16

Imm₃₂

29h

BIT Ra,#imm32

Addr₁₂

35h

BIT Ra,zp,Rb

Addr₁₂

21h

BIT Ra, (zp,Rb)

Addr₁₂

31h

BIT Ra, (zp),Rb

Addr₃₂

2Dh

BIT Ra,abs

Addr₃₂

3Dh

BIT Ra,abs,Rb

~₄

32h

BIT Ra, (Rb)

Load and Store Instructions

Arithmetic and logical instructions can take a memory operand as the third operand of the instruction. This effectively turns all these instructions into load instructions. Hence there isn’t an explicit load instruction. The OR or EOR instructions can readily be used to perform a load operation.

Because addresses are word addresses, the address field in the instructions is normally shifted left twice resulting in a 34 bit data address. The only exception to this is the byte load and store instructions.

Flags: n z

Bytes

Imm₈

05h

LD Rt,#imm8

Imm₁₆

19h

LD Rt,#imm16

Imm₃₂

09h

LD Rt,#imm32

Addr₁₂

15h

LD Rt,zp,Rb

Addr₁₂

01h

LD Rt, (zp,Rb)

Addr₁₂

11h

LD Rt, (zp),Rb

Addr₃₂

0Dh

LD Rt,abs

Addr₃₂

1Dh

LD Rt,abs,Rb

~₄

12h

LD Rt, (Rb)

LD is an alternate mnemonic for the OR instruction where register Ra is zero.

LB	Flags: n z							Bytes
		Addr₁₂	Rt	Rb	Ra	B5h	LB Rt,Ra,zp,Rb	4
	Addr₃₂			Rt	Ra	ADh	LB Rt,Ra,abs	6
Addr₃₂			Rt	Rb	Ra	BDh	LB Rt,Ra,abs,Rb	7

LB is an alternate mnemonic for the ORB instruction where register Ra is zero.

LDA	Flags: n z										Bytes
				Imm₈			1	0	05h	LD Rt,#imm8	3
		Imm₁₆					1	0	19h	LD Rt,#imm16	4
	Imm₃₂						1	0	09h	LD Rt,#imm32	6
		Addr₁₂			1		Rb	0	15h	LD Rt,zp,Rb	4
		Addr₁₂			1		Rb	0	01h	LD Rt, (zp,Rb)	4
		Addr₁₂			1		Rb	0	11h	LD Rt, (zp),Rb	4
	Addr₃₂						Rt	0	0Dh	LD Rt,abs	6
Addr₃₂					1		Rb	0	1Dh	LD Rt,abs,Rb	7
			~₄			1	Rb	0	12h	LD Rt, (Rb)	3

LDA is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is one.

LDX	Flags: n z										Bytes
				Imm₈			2	0	05h	LDX #imm8	3
		Imm₁₆					2	0	19h	LDX #imm16	4
	Imm₃₂						2	0	09h	LDX #imm32	6
		Addr₁₂			2		Rb	0	15h	LDX zp,Rb	4
		Addr₁₂			2		Rb	0	01h	LDX (zp,Rb)	4
		Addr₁₂			2		Rb	0	11h	LDX (zp),Rb	4
	Addr₃₂						Rt	0	0Dh	LDX abs	6
Addr₃₂					2		Rb	0	1Dh	LDX abs,Rb	7
			~₄			2	Rb	0	12h	LDX (Rb)	3

LDX is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is two.

LDY	Flags: n z										Bytes
				Imm₈			3	0	05h	LDY #imm8	3
		Imm₁₆					3	0	19h	LDY #imm16	4
	Imm₃₂						3	0	09h	LDY #imm32	6
		Addr₁₂			3		Rb	0	15h	LDY zp,Rb	4
		Addr₁₂			3		Rb	0	01h	LDY (zp,Rb)	4
		Addr₁₂			3		Rb	0	11h	LDY (zp),Rb	4
	Addr₃₂						Rt	0	0Dh	LDY abs	6
Addr₃₂					3		Rb	0	1Dh	LDY abs,Rb	7
			~₄			3	Rb	0	12h	LDY (Rb)	3

LDY is an alternate mnemonic for the OR instruction where register Ra is zero and register Rt is three.

Flags: none

Bytes

Addr₁₂

95h

ST Ra,zp,Rb

Addr₁₂

81h

ST Ra, (zp,Rb)

Addr₁₂

91h

ST Ra, (zp),Rb

Addr₃₂

8Dh

ST Ra,abs

Addr₃₂

9Dh

ST Ra,abs,Rb

~₄

92h

ST Ra, (Rb)

SB	Flags: none							Bytes
		Addr₁₂	0	Rb	Ra	74h	SB Ra,zp,Rb	4
	Addr₃₂			0	Ra	9Ch	SB Ra,abs	6
Addr₃₂			0	Rb	Ra	9Eh	SB Ra,abs,Rb	7

STA

Flags: none

Bytes

Addr₁₂

95h

STA zp,Rb

Addr₁₂

81h

STA (zp,Rb)

Addr₁₂

91h

STA (zp),Rb

Addr₃₂

8Dh

STA abs

Addr₃₂

9Dh

STA abs,Rb

~₄

92h

STA (Rb)

STA is an alternate mnemonic for ST where the register to be stored is R1 (the accumulator).

STX

Flags: none

Bytes

Addr₁₂

95h

STX zp,Rb

Addr₁₂

81h

STX (zp,Rb)

Addr₁₂

91h

STX (zp),Rb

Addr₃₂

8Dh

STX abs

Addr₃₂

9Dh

STX abs,Rb

~₄

92h

STX (Rb)

STX is an alternate mnemonic for ST where the register to be stored is R2 (the x index register). There are also additional short-hand forms for the STX instruction.

STY

Flags: none

Bytes

Addr₁₂

95h

STY zp,Rb

Addr₁₂

81h

STY (zp,Rb)

Addr₁₂

91h

STY (zp),Rb

Addr₃₂

8Dh

STY abs

Addr₃₂

9Dh

STY abs,Rb

~₄

92h

STY (Rb)

STY is an alternate mnemonic for ST where the register to be stored is R3 (the y index register). There are also additional short-hand forms for the STY instruction.

Shift Operations / Read-modify-write memory operations.

ASL	Flags: c n z							Bytes
						0Ah	ASL acc	1
				Rt	Ra	06h	ASL Rt,Ra	2
			Addr₁₂		Rb	16h	ASL zp,Rb	3
		Addr₃₂				0Eh	ASL abs	5
	Addr₃₂			Rb	0	1Eh	ASL abs,Rb	6

ROL	Flags: c n z							Bytes
						2Ah	ROL acc	1
				Rt	Ra	26h	ROL Rt,Ra	2
			Addr₁₂		Rb	36h	ROL zp,Rb	3
		Addr₃₂				2Eh	ROL abs	5
	Addr₃₂			Rb	0	3Eh	ROL abs,Rb	6

LSR	Flags: c n z							Bytes
						4Ah	LSR acc	1
				Rt	Ra	46h	LSR Rt,Ra	2
			Addr₁₂		Rb	56h	LSR zp,Rb	3
		Addr₃₂				4Eh	LSR abs	5
	Addr₃₂			Rb	0	5Eh	LSR abs,Rb	6

ROR	Flags: c n z							Bytes
						6Ah	ROR acc	1
				Rt	Ra	66h	ROR Rt,Ra	2
			Addr₁₂		Rb	76h	ROR zp,Rb	3
		Addr₃₂				6Eh	ROR abs	5
	Addr₃₂			Rb	0	7Eh	ROR abs,Rb	6

INC	Flags: n z							Bytes

				Rt	Ra	E6h	INC Rt,Ra	2
			Addr₁₂		Rb	F6h	INC zp,Rb	3
		Addr₃₂				EEh	INC abs	5
	Addr₃₂			Rb	0	FEh	INC abs,Rb	6

DEC	Flags: n z							Bytes

				Rt	Ra	C6h	DEC Rt,Ra	2
			Addr₁₂		Rb	D6h	DEC zp,Rb	3
		Addr₃₂				CEh	DEC abs	5
	Addr₃₂			Rb	0	DEh	DEC abs,Rb	6

X index register short-form instructions.

LDX	Flags: n z							Bytes
		Immediate₃₂				A2h	LDX #i32	5
			Immediate₁₆			B2h	LDX #i16	3
				Immediate₈		A6h	LDX #i8	2
			Addr₁₂		Rb	B6h	LDX zp,Rb	3
		Addr₃₂				AEh	LDX abs	5
	Addr₃₂			Rb	0	BEh	LDX abs,Rb	6
STX	Flags:							Bytes
			Addr₁₂		Rb	96h	STX zp,Rb	3
		Addr₃₂				8Eh	STX abs	5
CPX	Flags: c n z							Bytes
		Immediate₃₂				E0h	CPX #i32	5
			Addr₁₂		Rb	E4h	CPX zp,Rb	3
		Addr₃₂				ECh	CPX abs	5
INX	Flags: n z					E8h	INX	1
DEX	Flags: n z					CAh	DEX	1
PHX	Flags:					DAh	PHX	1
PLX	Flags:					FAh	PLX	1

Y index register short-form instructions.

LDY	Flags: n z							Bytes
		Immediate₃₂				A0h	LDY #i32	5
			Addr₁₂		Rb	B4h	LDY zp,Rb	3
		Addr₃₂				ACh	LDY abs	5
	Addr₃₂			Rb	0	BCh	LDY abs,Rb	6
STY	Flags:							Bytes
			Addr₁₂		Rb	94h	STY zp,Rb	3
		Addr₃₂				8Ch	STY abs	5
CPY	Flags: c n z							Bytes
		Immediate₃₂				C0h	CPY #i32	5
			Addr₁₂		Rb	C4h	CPY zp,Rb	3
		Addr₃₂				CCh	CPY abs	5
INY	Flags: n z					C8h	INY	1
DEY	Flags: n z					88h	DEY	1
PHY	Flags:					5Ah	PHY	1
PLY	Flags:					7Ah	PLY	1

Flow Control Instructions

JMP	Flags:							Bytes	Cyc
		Address₃₂				5Ch	JMP abs	5	2
				Address₁₆		4Ch	JMP abs	3	2
		Address₃₂				6Ch	JMP (abs)	5	3
		Address₃₂				7Ch	JMP (abs,x)	5	3
JSR	Flags:							Bytes
		Address₃₂				22h	JSR abs	5	3
				Address₁₆		20h	JSR abs	3	3
		Address₃₂				FCh	JSR (abs,x)	5	4
BSR				Disp₁₆		62h	BSR	3	3
RTS	Flags:					60h	RTS	1	3
RTI	Flags: z n c v b d i					40h	RTI	1	4
BRA	Flags:				Disp₈	80h	BRA disp	2	2
BEQ	Flags:				Disp₈	F0h	BEQ disp	2	2
BNE	Flags:				Disp₈	D0h	BNE disp	2	2
BPL	Flags:				Disp₈	10h	BPL disp	2	2
BMI	Flags:				Disp₈	30h	BMI disp	2	2
BVS	Flags:				Disp₈	70h	BVS disp	2	2
BVC	Flags:				Disp₈	50h	BVC disp	2	2
BCS	Flags:				Disp₈	B0h	BCS disp	2	2
BCC	Flags:				Disp₈	90h	BCC disp	2	2
BEQ	Flags:		Disp₁₆		01h	F0h	BEQ disp	4	2
BNE	Flags:		Disp₁₆		01h	D0h	BNE disp	4	2
BPL	Flags:		Disp₁₆		01h	10h	BPL disp	4	2
BMI	Flags:		Disp₁₆		01h	30h	BMI disp	4	2
BVS	Flags:		Disp₁₆		01h	70h	BVS disp	4	2
BVC	Flags:		Disp₁₆		01h	50h	BVC disp	4	2
BCS	Flags:		Disp₁₆		01h	B0h	BCS disp	4	2
BCC	Flags:		Disp₁₆		01h	90h	BCC disp	4	2
BRL	Flags:			Disp₁₆		82h	BRL disp	3	2
BRK	Flags: b					00h	BRK	1	5
NOP	Flags:					EAh	NOP	1	2
STP	Flags:					DBh	STP	1	2
WAI	Flags:					CBh	WAI	1	2

The STP instruction stops the processor clock until an NMI or RESET occurs.

The WAI instruction waits until an interrupt (NMI/IRQ) occurs.

Stack push and pop operations.

PHP	Flags:			08h	PHP	1
PHA	Flags:			48h	PHA	1
PHX	Flags:			DAh	PHX	1
PHY	Flags:			5Ah	PHY	1
PUSH	Flags:	~₄	Ra	0Bh	PUSH Ra	2
PLP	Flags: z c v n i b d			28h	PLP	1
PLA	Flags:			68h	PLA	1
PLX	Flags:			FAh	PLX	1
PLY	Flags:			7Ah	PLY	1
POP	Flags:	Rt	~₄	2Bh	POP Rt	2

CLC	Flags: c	18h	CLC	1	2
SEC	Flags: c	38h	SEC	1	2
CLV	Flags: v	B8h	CLV	1	2
CLI	Flags: i	58h	CLI	1	2
SEI	Flags: i	78h	SEI	1	2
CLD	Flags: d	D8h	CLD	1	2
SED	Flags: d	F8h	SED	1	2
EMM	Flags: m	FBh	EMM	1	2

TAX	Flags: n z				AAh	TAX	1
TXA	Flags: n z				8Ah	TXA	1
TAY	Flags: n z				A8h	TAY	1
TYA	Flags: n z				98h	TYA	1
TAS	Flags:				1Bh	TAS	1
TSA	Flags: n z				3Bh	TSA	1
TYX	Flags: n z				BBh	TYX	1
TXY	Flags: n z				9Bh	TXY	1
TSX	Flags: n z				BAh	TSX	1
TXS	Flags:				9Ah	TXS	1
TRS	Flags:	Spr	Ra		8Bh	TRS Ra,spr	2
TSR	Flags: n z	Rt		Spr	ABh	TSR spr,Rt	2