Butterfly SoC - Demo System on a Chip


The Butterfly demo system has been implemented on a BurchEd B5 FPGA board. A RAM module is connected to ports A and B, and an IO module is connected to port C. The programmable PLL clock must also be set for a clock frequency of 57.27272MHz. The following clock jumpers must be shorted: V3,6,7,8; S1,2; and R0,1,3,5,6 the remaining jumpers are open.


System Characteristics

The system clock runs at 28.636MHz although it could run faster. This clock frequency was chosen as convenient for generating video timing signals. External asynchronous static RAM is used for system memory and is shared between the cpu, video and audio controllers in a pipelined fashion. The cpu and video controller are each provided with about one-third of the memory bus bandwidth. Memory bus bandwidth is about 28.636MHz x 16 bits or 57MB/s.

On power-on a 40x25 text mode is selected. The video controller supports various resolutions, but the memory system limits the usable modes. 64 colors are supported (two bits each for red, blue and green). There are eight 24x21 sprites available, sprites are limited to eight colors. More information on the video controller can be found here (vgavic)

There is a partially debugged and tested SID audio core (the filter isn't tested yet), containing four ADSR channels supporting wave table synthesis. More information on the audio core can be found here (bcSID). The SID currently outputs sounds directly to a 12 bit delta-sigma DAC (The DAC requires external hardware which is assumed to be connected to the buzzer signal on the IO module).

About 70% of the LUT's in the FPGA are used, so there is room for some more goodies yet. There are a few block rams available, and these will likely be used for a processor cache.


System Memory Map

Address Usage
$0000_0000 - $FFFF_CFFF ram area - 128k x 16 bit - multiple images
$0000_0800 - $0000_1800 default text screen area
$FFFF_FC00 - $FFFF_FFFF boot rom - contains serial download routine

character ram - contains character glyphs for default screen chars

$FFFF_C000 - $FFFF_CFFF sprite image area - note ram underlays this area
$FFFF_DF00 - $FFFF_DFFF SID - audio controller circuit register area
$FFFF_DD00 - $FFFF_DDFF video controller circuit register area
$FFFF_DC00 - $FFFF_DFFF peripheral circuit register area (further broken down)
$FFFF_DC40 - $FFFF_DC4F system time slice generator circuit (ts_timer peripheral)
$FFFF_DC50 - $FFFF_DC5F ascii keyboard interface (PS2KbdToAscii peripheral)
$FFFF_DC60 - $FFFF_DC6F mouse interface (PS2kbd peripheral )
$FFFF_DC70 - $FFFF_DC7F serial uart interface (bc_uart3 peripheral)
$FFFF_DC80 - $FFFF_DC8F LED - used to flash LED
$FFFF_DC90 - $FFFF_DC9F spic - simple priority interrupt controller
$FFFF_DCA0 - $FFFF_DCAF random number generator (rand peripheral)

Note that only the low order 18 address bits are implemented in the system. This is sufficient to decode the above memory map.


Development Tools

Currently all software is being written in Butterfly assembler code which is a cross macro assembler that runs on the PC. A port of the LCC 'C' compiler is also available so it is possible to program in 'C' if so desired. (It's included in the .zip file below). Note: it helps to set "set include=" when using the LCC compiler.



boot_rom.asm    - Working source code sample listing of the boot ROM including an intel hex file downloader

The Intel hex downloader now supports linear address records, so it is possible to download anywhere in memory.

There is a demo program written in a combination of 'C' and assembler that does a few things like display messages and switch graphics modes. Note you may have to press several keys before the program runs (it looks like it's sitting at a blue screen, but it's really waiting for keyboard input.)

Tiny BASIC has been ported !


System Boot

The system boots from an internal boot ROM. The boot ROM contains only the bare minimum required to allow the system to further boot from a downloaded file. It clears the screen, displays a power on message, sounds a tone on the speaker, then enters the serial download routine. While waiting for a serial download, an indicator flashes on the screen. The serial interface uses hardware(cts, rts)  flow control, runs at 38k baud, 8 bits no parity, one start and one stop bit. Once a further boot program is loaded, the ROM jumps to the downloaded program to continue the boot process or run another program (the program start address is assumed to be located at $b000).

The keyboard interface recognizes the CTRL-ALT-DEL sequence which resets the entire system.


FPGA image

This is the bit-file that can be loaded into the FPGA to turn an appropriately connected BurchEd system into the Butterfly SoC demo system. It is contained in the zip file below.



bfSoC.zip - assembler, .mcs file, and boot rom listing


In the works

- a loadable BIOS

- a port of BASIC